1. Field of the Invention
The present invention generally relates to a memory circuit and, more particularly, to a memory circuit adapted to high speed memory access in which the pipeline processing is realized.
2. Description of the Prior Art
Logic devices are required to operate with high speed. For this purpose, pipeline processing has been widely adopted in logic circuits. In a conventional memory circuit in which a RAM (random access memory) is directly connected to a data bus for a logic device in a pipeline control system, transfer of data to be written on the data bus and writing of the transferred data into the memory are carried out in one stage. In the same manner, reading of data from the memory and transfer of the read data on the data bus are also carried out in one stage. That is, the transfer of the data is carried out without dividing the writing of the data into the memory and the reading of the data from the memory, respectively, into different stages of the pipeline control. This is because the writing processing and the reading processing are opposite to each other in order, so that the continuity of the pipe line processing is not maintained, if the transfer of the data is separated from the data writing into the memory and the data reading from the memory.
In this conventional memory circuit, there is a disadvantage in that an average access time is not shortened to be less than the sum of a data transfer time and a memory processing (writing or reading) time at each stage of the pipeline control, because the data transfer and the memory processing are carried out in one stage. The detail of the disadvantage will be explained in the later description to be made by referring to the drawings.